Digital computers and the like often include a plurality of very large scale integration (VLSI) circuits which are interconnected for binary communications by a bus or a transmission line. Transmitters and receivers interface the VLSI components of such systems to the transmission lines. The transmission lines may have their opposite ends terminated at their characteristic impedance. This results in the power internally dissipated by the driver being proportional to the nominal voltage swing of the binary signal it applies to the transmission line.
Complementary metal-oxide-semiconductor (CMOS) technology digital circuits are attractive for use in digital computers because of lower power consumption and hence lower cooling requirements, and lower construction cost. However, CMOS chips are inferior to emitter-coupled logic (ECL) components in both intra-chip and inter-chip operation speeds. The aforementioned advantages of ECL chips are mainly due to a lower voltage swing between logic low and logic high levels, and fewer transmission line effects resulting from impedance matching. The rail-to-rail voltage swing of standard CMOS circuits tends to cause the transmitters of such circuits to dissipate excessive amounts of power internally whenever the transmitters are working into low impedance loads such as terminated transmission lines.
The trend to faster CMOS technologies allows the design of very fast on-chip logic gates. This high performance often ends, however, at the die pads where typical modern digital CMOS devices drive their output pads with a simple CMOS inverter. The inverter, which swings the output pad from ground to rail voltage, is large in order to drive its capacitive output load quickly. The large output inverter is itself driven by a string of scaled inverters, typically three stages, to scale the internal on-chip gate signals to a drive level capable of quickly switching the large external capacitance.
This approach was very successful for the 3-4 micrometer channel-length CMOS generations, because the rise time of the final output inverter was limited to a 5-10-nanosecond transition time. Since this transition time was relatively slow, the traces on a typical printed circuit board could be successfully modeled as lumped capacitive loads. However, the disparity between on-chip processing speeds and inter-chip communication speed becomes increasingly troublesome as CMOS technology scales into the sub-micrometer channel length region. This is because modern CMOS technology, with sub-micrometer channel lengths, results in output switching times in the sub-nanosecond range. Printed circuit traces can no longer be treated as purely capacitive loads when driven by sub-nanosecond rise-time signals. The large junction capacitance associated with CMOS circuits thus limits the speed of the bus by loading down the bus line. Prior art designers have approached this problem by explicitly slowing the turn-on of output transistors. While this slows the rise time of the signal and allows the load to be treated as purely capacitive, it also slows the arrival of the output signal at its destination.
Designers of prior art circuits also attempted to solve this signaling problem with the use of terminated transmission lines as an interconnection technique. Terminated transmission lines have many advantages over driving capacitive loads. However, sizing the final output driver stage sufficiently large to allow driving a terminated transmission line is problematic because it requires large and slow predriver stages which dissipate large amounts of power. Designers of prior art circuits reduce this power dissipation problem by utilizing a low voltage logic swing transmitter and receiver. However, there remains a need to reduce capacitive loading effects of the transistor drivers used to drive the voltages on the transmitting end of the bus in order to increase the data transfer speed of data buses used with CMOS chips.